1. Field of the Invention
The present invention is related in general to the field of semiconductor device assembly and packaging, and more specifically to fabricating integrated circuit (IC) devices that are protected against potential damage caused by moisture, contamination, and stress induced defects such as cracks and delamination when incorporated into wafer level chip scale packages.
2. Description of the Related Art
It is well known to use a scribe seal (which may also be referred to as a die seal, an edge seal, or a seal ring) to protect a die against potential damage caused by stress induced defects such as crack formation and delamination formed during processes such as sawing, wirebonding or other assembly processes, soldering, or during rigorous environmental testing. The scribe seal, which is typically formed around a perimeter of the die, is disposed between the die and a saw street (may also be referred to as a scribe street or a dicing street).
It is also well known that stress induced defects such as cracks and delamination are likely to occur near die corners where susceptibility to die failure from such defects is highest. Conventional techniques to reduce damage caused by stress include providing a die layout having a sloped or chamfered corner area rather than a die layout having a sharp corner, e.g., a 90 degree corner, and providing redundant scribe seals for added protection. However, conventional techniques may still be inadequate to protect the die corners, which are formed during the sawing. Due to their porosity, brittleness, and low strength, low-k dielectric layers commonly used in the back end of line (BEOL) stack are particularly susceptible to fracture during the sawing process and blisters or delamination due to mechanical stresses from subsequent packaging, moisture absorption, or thermal cycling. Die failure is most likely to occur at or near the die corners where die stresses are highest and die edge defects can potentially rupture the scribe seal(s).
These issues have been recognized, and various approaches and structures to provide barriers to contamination and moisture and to arrest crack propagation and absorb stresses and damage have been proposed. These earlier approaches, some of which can be quite elaborate, are nevertheless still found to be insufficient to prevent cracks and delamination from occurring, especially in the corners of semiconductor dice that contain low-k dielectric materials and that subsequently undergo processes related to wafer level chip scale packaging (abbreviated WLCSP, WL-CSP, or WCSP). The problems are particularly severe in WLCSP that utilize redistribution layers (RDL) to remap the positions of interconnect solder bumps or balls from the locations of pads on the die, since there are more and thicker package insulating layers required to effect this remapping that are applied directly to the surface of the die, and as a result of having different coefficient of thermal expansion (CTE) from the die, induce significant tensile peel stress to the die edge. Thus there remains a need for improved structures for scribe seals and for methods of fabricating and reinforcing semiconductor devices used in wafer level chip scale packaging.